1. Field of the Invention
The present invention relates to an image signal processing circuit which converts a serial image signal into parallel form, performs digital-analog conversion on each parallel image signal, and amplifies and outputs it, and a image display apparatus and an electronic apparatus using the image signal processing circuit. Furthermore, the present invention relates to a method of adjusting the amplitude of an analog image signal which is output from a plurality of digital-analog converters. The image signal in the present invention is handled as being equivalent to a picture signal.
2. Description of the Related Art
For example, when performing liquid-crystal display, as the number of pixels of a display screen increases, the transfer frequency of pixel data increases, and the transfer frequency becomes 40 MHz in SVGA (800xc3x97600 pixels) having a standard pixel density, and becomes 65 MHz in XGA (1024xc3x97768 pixels) having a high pixel density. Meanwhile, the response frequency of writing to a liquid-crystal element is 7 to 8 MHz when a TFT (Thin Film Transistor) is used as a sampling switch. Therefore, a serial image signal is converted into N parallel signals, and the transfer frequency is lowered by 1/N to a frequency at which response is possible by a TFT (see Japanese Unexamined Patent Publication No. 8-352358, WO97/08677, and WO97/49080).
Here, the serial-parallel conversion of an image signal is called xe2x80x9cphase expansionxe2x80x9d. As shown schematically in FIG. 14, serial input data D has serial image data a1, a2, . . . which are transferred in accordance with a reference clock CLK of, for example, 40 MHz. In the phase-expansion circuit, image data a1, a2, . . . are expanded by a shift register and a latch circuit so that its data transfer cycle becomes six times as high as that of the original, and the phase-expanded image signals D1, D2, . . . D6 are output in parallel.
The method of FIG. 14 is called xe2x80x9csix-phase expansionxe2x80x9d and is used in the case of SVGA having low pixel density. The writing frequency in this case is 6.7 MHz. Meanwhile, in the case of XGA having a high pixel density, 12-phase expansion is used, and the writing frequency at this time is 5.4 MHz.
A liquid-crystal display apparatus using a conventional image signal processing circuit including this phase-expansion circuit is shown in FIG. 15. In FIG. 15, a scanning signal from a scanning circuit 501 and a data signal from a image signal processing circuit 502 are provided to a liquid-crystal panel 500, causing the liquid-crystal panel 500 to be driven.
The image signal processing circuit 502 comprises a phase-expansion circuit 503, a polarity-inversion circuit 504, digital-analog converters (hereinafter abbreviated as D/A converters) 511 to 516, and operational amplifiers 551 to 556.
Variable resistors 521 to 526 which adjust the output amplitude of an analog signal output from the D/A converters 511 to 516 are connected to parts of output lines 511A to 516A of the D/A converters 511 to 516, respectively. Also, a bias signal line 505 is connected in common to the negative terminals of the operational amplifiers 551 to 556, and the output lines 511A to 516A of the D/A converters 511 to 516 are respectively connected to the positive terminals.
Gain setting resistors 531 to 536, and 541 to 546 are connected to the operational amplifiers 551 to 556, respectively. Of these, the gain setting resistors 541 to 546 are formed of variable resistors.
A case will now be considered in which the same halftone display is performed on the entire screen of the liquid-crystal panel shown in FIG. 15. The outputs of the operational amplifiers 551 to 556 are connected to the respective signal lines along the vertical direction of the liquid-crystal panel 500. For this reason, when, for example, a voltage different from those of the operational amplifiers 552 to 556 is output from only the operational amplifier 551, patterns in the form of longitudinal stripes appear every six lines on the liquid-crystal panel 500, and the display quality is degraded.
Therefore, in the conventional image signal processing circuit 502 shown in FIG. 15, the variable resistors 521 to 526 connected to the D/A converters 511 to 516 and the variable resistors 541 to 546 connected to the operational amplifiers 551 to 556 are each adjusted manually.
In recent years, as the liquid-crystal display screen has become larger, of a higher definition or a color-picture display, the number of pixels tends to increase, and the number of variable resistors shown in FIG. 15 has increased with the increase in the number of pixels.
For example, in a color display of XGA, the number of variable resistors becomes:
12(number of phase expansions)xc3x973(R, G, B)xc3x972(number of variable resistors in one line)=72
Since a number of such variable resistors are required, not only is the cost of parts increased, but also manpower and time are necessary for manual resistance value adjustments. This results in an increased cost of the image signal processing circuit or the liquid-crystal display apparatus. Also, since the adjusted resistance value varies with time, this might cause luminance variations to gradually occur, and improvements must be made from the viewpoint of picture quality.
Accordingly, an object of the present invention is to provide an image signal processing circuit in which the number of variable resistors is decreased to lessen the operation of adjusting the resistance value, thereby resulting in decreased cost, and a image display apparatus and an electronic apparatus using the image signal processing circuit.
Another object of the present invention is to provide an image signal processing circuit in which automatic adjustment of the resistance value is made possible and the occurrence of luminance variation with time can be prevented, and an image display apparatus and an electronic apparatus using the image signal processing circuit.
A further object of the present invention is to provide an image signal processing circuit in which the mounting area of resistors is reduced and further, a S/N ratio can be improved and radiation noise can be reduced, and an image display apparatus and an electronic apparatus using the image signal processing circuit.
Still a further object of the present invention is to provide a method capable of adjusting quickly and accurately the output amplitude of a plurality of digital-analog converters.
An image signal processing circuit in accordance with the present invention provides an image signal processing circuit, comprising:
a serial-parallel converter for converting a serial digital image signal into N parallel digital image signals;
N digital-analog converters for converting the N parallel digital image signals into respective analog image signals;
N amplifiers for amplifying and outputting the analog image signals from the N digital-analog converters, respectively; and
N sets of gain setting resistors, connected to the respective N amplifiers, for setting respective gains of the N amplifiers,
wherein each of the N sets of gain setting resistors includes first and second resistors, and the first and second resistors are formed on a first substrate in the same manufacturing step so that the resistance value of each of the N sets of gain setting resistors need not be adjusted.
In the present invention, the resistance ratio of the first and second resistors which constitute a gain setting resistor is substantially the same for each set without requiring any adjustment. Since the first and second resistors are formed on the same substrate in the same manufacturing step, manufacturing is possible with high accuracy in such a manner as to be dependent upon, for example, mask accuracy during exposure. When the resistance ratio of the first and second resistors of each set is substantially the same, the gain of N amplifiers becomes substantially the same without requiring any adjustment. Therefore, it is possible to prevent luminance variations in the form of longitudinal stripes from occurring for each of the parallel output lines on the display screen.
It is possible to further provide N amplitude adjusting resistors, connected to respective output lines of N digital-analog converters, for adjusting the amplitude of each analog image signal. In this case, each resistance value of each of N amplitude adjusting resistors is adjusted by laser trimming.
As a result of the above, the amplitude of the respective analog image signals which are input to N amplifiers is substantially the same. Also from this fact, it is possible to prevent luminance variations in the form of longitudinal stripes from occurring for each parallel output line on the display screen. In particular, when compared to a conventional technology that manually adjusts a moving part of a variable resistor by means of a jig, because the automatic adjustment of a resistance value becomes possible, an operation load of a laser-trimmed resistor is reduced greatly. Also, since resistance value variations with time do not occur in the laser-trimmed resistor, there is no such occurrence of luminance variation with time and degradation of image quality.
In the present invention, it is possible to provide a digital polarity-inversion circuit between a serial-parallel converter and N digital-analog converters, or an analog polarity-inversion circuit between N digital-analog converters and N amplifiers.
In this case, each of the N amplifiers is formed by an operational amplifier having first and second input terminals, an analog image signal is input to the first input terminal of the operational amplifier, and a polarity-inverting bias signal is input to the second input terminal of the operational amplifier.
As a result of the above, since the level-shift amount of the polarity-inverting bias signal is determined by the resistance ratio of the first and second resistors, the level-shift amount can be substantially the same with respect to N amplifiers.
It is possible to form k (1 less than kxe2x89xa6N) sets of gain adjusting resistors on the first substrate. In other words, it is possible to form the first and second resistors which constitute two or more sets of gain adjusting resistors on the first substrate. As a result of the above, the accuracy of the resistance ratio of k sets of gain adjusting resistors is further improved.
The first substrate and k sets of gain adjusting resistors preferably include a circuit package (a first circuit package) which is housed inside a resin mold with a plurality of terminals (first terminals) connected to the k sets of gain adjusting resistors being exposed. As a result of the above, the influence of environmental variations upon the resistance ratio of the k sets of gain adjusting resistors is reduced.
It is possible to form k amplifiers into a hybrid IC by providing a second circuit package which is housed inside a resin mold with a plurality of second terminals connected to k amplifiers being exposed, and a main substrate which mounts the first circuit package and the second circuit package. This main substrate has wiring patterns formed on both sides and a plurality of through holes which pass through the main substrate. The first circuit package is mounted on one side of the main substrate, the second circuit package is mounted on the other side, and a plurality of first and second terminals are connected to each other through the plurality of through holes. As a result of the above, the wiring that connects the amplifiers to the gain setting resistors does not intersect, and further, the wiring length can be shortened. Therefore, noise is not easily superposed onto the wiring that connects the amplifiers to the gain setting resistors, causing the S/N ratio to be improved. Furthermore, a high-frequency wave is not easily radiated from the wiring that connects the amplifiers to the gain setting resistors, making it possible to reduce the influence of noise upon peripheral circuits.
The first circuit package and the second circuit package are preferably mounted at opposing positions with the main substrate in between. The length of wiring that connects the amplifier to the gain setting resistor can be minimized.
It is preferable that k digital-analog converters and k amplitude adjusting resistors be housed within a third circuit package and the third circuit package be mounted on the main substrate. As a result of the above, the image processing circuit can be formed into an even smaller size.
In another embodiment of the present invention, k (1 less than k xe2x89xa6N) first resistors may be formed on a first substrate in the same manufacturing step, and k second resistors may be formed on a second substrate in the same manufacturing step. As a result of the above, each resistance value of the k first resistors becomes substantially the same, and each resistance value of the k second resistors becomes substantially the same. As a result, the resistance ratio of k sets of gain setting resistors can be substantially the same.
The image display circuit of the present invention comprises an image signal processing circuit having the above-described construction, and an electro-optical device driven in accordance with an analog image signal output from this image signal processing circuit. The electronic apparatus of the present invention comprises this image display apparatus. On the display screens of these, luminance variations in the form of longitudinal stripes do not occur for each of the parallel output lines.
The present invention provides a method of adjusting an amplitude of an analog image signal output from each of a plurality of digital-analog converters, the method comprising the steps of:
a first step of laser-trimming a first load resistor connected to an arbitrary first digital-analog converter from among the plurality of digital-analog converters; and
a second step of laser-trimming a second load resistor connected to an arbitrary second digital-analog converter from among the plurality of digital-analog converters,
wherein the first step includes a step in which the first load resistor is laser-trimmed so that an output voltage from the first digital-analog converter when a predetermined digital signal is input to the first digital-analog converter is within a first allowable range, and
the second step includes a step in which the second load resistor is laser-trimmed so that the potential difference between respective output voltages from the first and second digital-analog converters when the predetermined digital signal is input to the first and second digital-analog converters is within a second allowable range.
According to the method of the present invention, an output of the first digital-analog converter, which is a reference, and an output of the second digital-analog converter, which is an object for adjustment, are measured at the same time under equal environment temperature conditions. Therefore, it is possible to start laser trimming without waiting for the characteristics of the N digital-analog converters and the N amplitude adjusting resistors to reach temperature saturation.